Method for manufacturing a resin-sealed semiconductor device

ABSTRACT

A heat plate includes projections for supporting half-etched portions of first signal connection leads, respectively. A lead frame having a resin film mounted thereon is mounted on the heat plate, and thin metal wires are respectively connected to the half-etched portions of the first signal connection leads. Even when the thin metal wire is connected to the half-etched portion of each first signal connection lead, pressing force and heat can be effectively applied to the connection.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for manufacturing aresin-sealed semiconductor device including half-etched leads.

[0002] Recently, in order to deal with miniaturization of the electronicequipments, semiconductor components mounted on the electronicequipments need be mounted at a high density. In response to such aneed, improvement in performance as well as reduction in size andthickness of the semiconductor components have been accelerated.

[0003] Conventionally, in order to mount the semiconductor devices on aprinted board surface at a high density, a semiconductor chipincorporating elements such as transistors is sealed in a square orrectangular sealing resin, thereby forming a resin-sealed semiconductordevice. QFP (quad flat package) technology, i.e., technology ofarranging a multiplicity of gull-wing-shaped external lead terminals onthe side surfaces of the package, has been widely used for such aresin-sealed semiconductor device. The QFP technology is also requiredto increase the number of external lead terminals in order to deal withimproved performance (improved LSI (Large Scale Integration)) of thesemiconductor chip. In this case, in order to increase the number ofexternal lead terminals without increasing the outside dimensions of aQFP, narrow-pitch QFPs having a terminal pitch of 0.3 mm are nowpartially used for practical applications. However, manufacturing andmounting of such a narrow-pitch QFP have not been successful due to theproblems such as reduced yield and degraded quality resulting frombending of the leads. Moreover, the QFP technology is encountering manyobstacles to reduction in size.

[0004] Recently, the following method was proposed in order to implementimprovement in performance as well as reduction in size and thickness:the lower portion of each lead is partially removed by half etching. Inthe resin sealing step, a resin film is pressed against the lowersurface of the whole lead frame so as to expose from the sealing resinthe lower portion of each lead except for the half-etched portion. Theexposed portion of each lead is used as an external terminal.

[0005] In the conventional resin-sealed semiconductor device includingleads each having a half-etched portion, wire bonding of the leads isgenerally conducted by connecting a thin metal wire to each lead at aposition right above an external terminal, that is, right above anon-half-etched portion, in order to effectively apply to the thin metalwire the pressing force required to connect the thin metal wire to thelead.

[0006] However, recent improvement in performance and reduction in sizeof the semiconductor devices is making it difficult to conduct wirebonding while preventing the metal wires connected to the respectiveleads from contacting each other. More specifically, during wirebonding, the tip of a bonding tool moves to form a complicated locus.Therefore, a substantial space is required between the metal wires, andalso crossing of the metal wires as viewed two-dimensionally must beprevented as much as possible.

[0007] Arranging the external terminals exposed from the back surface ofthe sealing resin (i.e., the lower portions of the leads) in a pluralityof lines so as to achieve a high mounting density of the externalterminals noticeably causes the aforementioned problems. For example,such arrangement results in a very narrow space between the metal wiresconnected to the leads at a position right above the respective externalterminals, or necessitates crossing of the thin metal wires. Inparticular, there may be a case where external terminals are to beprovided also under the semiconductor chip. In such a case, the thinmetal wires cannot be connected to the leads at a position right abovethe respective external terminals. Therefore, it is actually impossibleto satisfy such a requirement.

[0008] The steps prior to the resin sealing step may be conducted with aresin film attached in advance to a lead frame. In such a case, however,it is more difficult to apply to the half-etched portion of the lead thepressing force required to connect the thin metal wire to the lead.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to avoid the problemsassociated with wire bonding of a resin-sealed semiconductor devicewhile allowing for increase in the number of external terminals eachformed from a part of a corresponding lead.

[0010] A method for manufacturing a resin-sealed semiconductor deviceaccording to the present invention includes the steps of: (a) preparinga lead frame including a die pad on which a semiconductor chip ismounted, a frame arranged outside the die pad, and a plurality of leadsextending from the frame toward the die pad and each including ahalf-etched portion; (b) mounting on the die pad of the lead frame thesemiconductor chip including a plurality of electrode pads; (c) mountingthe lead frame having the semiconductor chip mounted thereon on a jigincluding projections for supporting the half-etched portions of theleads to which thin metal wires are respectively connected out of thehalf-etched portions of the plurality of leads; (d) connecting theelectrode pads of the semiconductor chip to the plurality of leads bythe thin metal wires, respectively; and (e) resin-sealing thesemiconductor chip, the die pad, the leads and the thin metal wires witha resin film being pressed against a lower surface of the lead frame. Inthe step (d), the half-etched portions to which the thin metal wires areconnected are supported by the projections of the jig, respectively.

[0011] According to this method, of the plurality of leads, each of theleads to which a thin metal wire is connected at the half-etched portionhas a corresponding projection of the jig located under the half-etchedportion when the thin metal wires are connected to the leads in the step(d). Accordingly, wire bonding can be reliably conducted with thepressing force effectively applied to the thin metal wire. Moreover,limitations on the position in each lead where the thin metal wire isconnected are reduced, enabling the number of leads to be increased orthe positions of the leads to be changed in various ways while avoidingthe problems in the wire bonding. This allows for reduction in size of aresin-sealed semiconductor device with improved performance.

[0012] The step (d) may be conducted with the heated jig. This enablesthe thin metal wires to be easily connected to the leads in a reliablemanner in the wire bonding step.

[0013] The resin film may be mounted to the lower surface of the leadframe prior to the step (c), and the step (d) may be conducted with theresin film being mounted to the lower surface of the lead frame. Thisenables the resin sealing step to be conducted with a plurality ofsemiconductor chips mounted in a single die cavity of a sealing mold,allowing the mounting step using the resin film to be conducted withimproved efficiency.

[0014] In the step (d), the jig including a vacuuming opening may beused to draw the resin film toward a surface of the jig by vacuuming.This enables the problems due to slacking in the resin film to beavoided.

[0015] In the step (d), the die pad of the lead frame may be raisedupward. This enables wire bonding to be conducted with the resin filmbeing stretched more reliably.

[0016] A material having a thermal expansion coefficient of 5 to 25×10ppm/° C. may be used as the resin film. This enables slacking in theresin film to be suppressed within a proper range even when the resinfilm is heated by the jig in the step (d).

[0017] In the step (a), an upper surface of the die pad of the leadframe may be located higher than respective upper surfaces of the leads.Preparing such a lead frame enables the leads to be extended to aposition under the semiconductor chip, whereby the range in which theexternal terminals may be arranged can be increased.

[0018] In the step (a), the plurality of leads of the lead frame may bearranged such that respective lower portions of the plurality of leadsexcept for the half-etched portions are arranged in a plurality of lineswhen viewed from a back surface of the sealing resin. This enablesmounting of a resin-sealed semiconductor device with improvedperformance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1A is a cross-sectional view of a resin-sealed semiconductordevice according to an embodiment of the present invention taken alongline Ia-Ia in FIG. 1B, and FIG. 1B is a bottom view of the resin-sealedsemiconductor device according to the embodiment of the presentinvention;

[0020]FIGS. 2A to 2E are cross-sectional views illustrating amanufacturing process of a resin-sealed semiconductor device accordingto an embodiment of the present invention;

[0021]FIG. 3A is a plan view of a region of a lead frame for packaging asingle semiconductor chip, FIG. 3B is a cross-sectional view taken alongline IIIb-IIIb in FIG. 3A, and FIG. 3C is a cross-sectional view takenalong line IIIc-IIIc in FIG. 3A;

[0022]FIG. 4A is a plan view of a lead frame and a semiconductor chipafter wire bonding, FIG. 4B is a cross-sectional view taken along lineIVb-IVb in FIG. 4A, and FIG. 4C is a cross-sectional view taken alongline Ivc-IVc in FIG. 4A;

[0023]FIGS. 5A to 5C are cross-sectional views specifically illustratingthe wire bonding step according to an embodiment of the presentinvention;

[0024]FIG. 6 is a cross-sectional view illustrating the wire bondingstep according to a first modification of the embodiment of the presentinvention;

[0025]FIG. 7 is a cross-sectional view illustrating the wire bondingstep according to a second modification of the embodiment of the presentinvention;

[0026]FIG. 8 is a cross-sectional view illustrating the wire bondingstep according to a third modification of the embodiment of the presentinvention;

[0027]FIG. 9 is a cross-sectional view illustrating the wire bondingstep according to a fourth modification of the embodiment of the presentinvention;

[0028]FIG. 10 is a cross-sectional view illustrating the wire bondingstep according to a fifth modification of the embodiment of the presentinvention;

[0029]FIG. 11 is a cross-sectional view illustrating the wire bondingstep according to a sixth modification of the embodiment of the presentinvention;

[0030]FIG. 12 is a cross-sectional view illustrating the wire bondingstep according to a seventh modification of the embodiment of thepresent invention; and

[0031]FIG. 13 is a bottom view of a resin-sealed semiconductor deviceaccording to an eighth modification of the embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032]FIG. 1A is a cross-sectional view of a resin-sealed semiconductordevice according to an embodiment of the present invention taken alongline Ia-Ia in FIG. 1B. FIG. 1B is a bottom view of the resin-sealedsemiconductor device according to the embodiment of the presentinvention.

[0033] As shown in FIGS. 1A and 1B, the resin-sealed semiconductordevice of the present embodiment includes a die pad 11, a multiplicityof first signal connection leads 14 a and a multiplicity of secondsignal connection leads 14 b both extending near the die pad 11, arather thick adhesive layer 17 formed on the die pad 11, a semiconductorchip 20 fixed to the die pad 11 by the adhesive layer 17 and including amultiplicity of electrode pads 21, thin metal wires 25 for electricallyconnecting the electrode pads 21 on the semiconductor chip 20 to thesignal connection leads 14 a, 14 b, respectively, and a sealing resin 30for sealing the die pad 11, signal connection leads 14 a, 14 b,semiconductor chip 20, thin metal wires 25 and the like. The lowerportion of each of the first and second signal connection leads 14 a, 14b is partially removed by half etching. The residual portion thatremains after half-etching the lower portion is herein referred to ashalf-etched portion Phe. The lower end face of the non-half-etchedportion of each of the first and second signal connection leads 14 a, 14b is exposed without being covered with the sealing resin 30. Theseportions are first and second external terminals 15 a, 15 b. Therespective tips of the first and second signal connection leads 14 a, 14b are located directly under the semiconductor chip 20. In other words,the semiconductor chip 20 overlaps the first and second signalconnection leads 14 a, 14 b as viewed two-dimensionally.

[0034] As shown in FIG. 1B, the die pad 11 and the first and secondexternal terminals 15 a, 15 b arranged in two lines are exposed from theback surface of the resin-sealed semiconductor device without beingcovered with the sealing resin 30, so that the respective lower surfacesof the first and second external terminals 15 a, 15 b serve asconnection surfaces with a mounting board such as a printed circuitboard.

[0035] In the resin sealing step described below, resin is introducedinto a die cavity with a resin film being attached to the lower surfaceof a lead frame. This prevents a resin bur resulting from excessiveresin from being formed at the exposed portion of the die pad 11 and therespective lower surfaces of the first and second external terminals 15a, 15 b in the resin sealing step, improving reliability of theconnection between the external terminals 15 a, 15 b and electrodes ofthe mounting board. Since a part of the sealing resin 30 is presentunder the respective half-etched portions Phe of the signal connectionleads 14 a, 14 b, the signal connection leads 14 a, 14 b are held withthe sealing resin 30 with improved holding power, resulting in improvingreliability of the resin-sealed semiconductor device.

[0036] According to the resin-sealed semiconductor device of the presentembodiment, the thin metal wires 25 are connected to the respectivehalf-etched portions Phe of the first signal connection leads 14 a. Asdescribed below, the thin metal wires 25 are connected to the firstsignal connection leads 14 a while making sure that the pressing forceapplied between the thin metal wires 25 and the first signal connectionleads 14 a works effectively. This allows for excellent reliability ofthe connection between the thin metal wires 25 and the signal connectionleads 14 a, 14 b.

[0037] Accordingly, the resin-sealed semiconductor device of the presentembodiment can be easily configured so as to avoid approach and crossingof the thin metal wires 25 when they are respectively connected to thesignal connection leads 14 a, 14 b, thereby reducing the positionallimitations on the external terminals. This enables increase in overallsize of the package of the resin-sealed semiconductor device to beavoided even when a relatively large semiconductor chip with improvedperformance is mounted.

[0038] In particular, in the present embodiment, the first and secondsignal connection leads 14 a, 14 b extend to the position right underthe semiconductor chip 20, and the first external terminals 15 a arearranged under the semiconductor chip 20. This particularly enables amultiplicity of external terminals to be arranged within a small areaeven when a relatively large semiconductor chip with improvedperformance is mounted, whereby a resin-sealed semiconductor device canbe provided which is suitable for increased density of the externalterminals, and reduced size and thickness of the semiconductor device.Note that, even when the external terminals are arranged outside thesemiconductor chip and the thin metal wires are connected to the signalconnection leads at a position right above the respective externalterminals, the signal connection leads are extended to the positionunder the semiconductor chip. This ensures that the sealing resin holdsa large region of each signal connection lead, allowing for improvedreliability.

[0039] Note that, in the present embodiment, the first and secondexternal terminals 15 a, 15 b are arranged in two lines at the backsurface of the resin-sealed semiconductor device. However, the externalterminals may be arranged in three or more lines.

[0040] In the resin-sealed semiconductor device of the presentembodiment, the first and second external terminals 15 a, 15 b and thedie pad 11 are exposed from the back surface of the sealing resin 30.Therefore, the external terminals 15 a, 15 b and the die pad 11 needonly be connected to the electrodes of the mounting substrate in orderto mount the resin-sealed semiconductor device of the present embodimenton the mounting substrate. This allows the external terminals 15 a, 15 bto be directly used as external electrodes, eliminating the need toadditionally provide a solder ball on each of the external terminalportions 15 a, 15 b for mounting on the mounting substrate. This is alsoadvantageous in terms of man-hour and manufacturing costs.

[0041] Hereinafter, the manufacturing process of the resin-sealedsemiconductor device in the present embodiment will be described. FIGS.2A to 2E are cross-sectional views illustrating the manufacturingprocess of the resin-sealed semiconductor device according to theembodiment of the present invention.

[0042] In the step of FIG. 2A, a lead frame 10 is prepared, and a resinfilm 40 is attached to the back surface of the lead frame 10. Althoughthe structure of the lead frame 10 is simplified in FIG. 2A, the leadframe 10 actually has a structure as described below. It should be notedthat the step such as wire bonding may be conducted without attachingthe resin film 40 to the lead frame in this stage, and the resin film 40may be attached to a sealing mold in the resin sealing step.

[0043] The resin film 40 serves as a mask for preventing the sealingresin from reaching particularly the back surface of the die pad 11 (inthe case where the die pad is exposed) and the back surface of the firstand second signal connection leads 14 a, 14 b in the resin sealing step,and also serves to fill the resin under the half-etched portions Phe.The presence of the resin film 40 enables a resin bur from being formedat the back surface of the die pad 11 (in the case where the die pad isexposed) and the back surface of the first and second signal connectionleads 14 a, 14 b. Moreover, in the resin sealing step, the sealing resinis introduced with the lower portion of each signal connection lead 14a, 14 b being pressed into the resin film 40. Thus, when the resinsealing is completed, the external terminals 15 a, 15 b of the signalconnection leads 14 a, 14 b project from the back surface of the sealingresin 30 by a prescribed height. In other words, a standoff as anexternal terminal is obtained, enabling the resin-sealed semiconductordevice to be mounted on the mounting substrate without providing anysolder ball as an external terminal.

[0044] The resin film 40 is desirably a film- or tape-like member thatis based on a resin primarily containing polyethylene terephthalate,polyimide, polycarbonate or the like, and that has an adhesive appliedthereon. The following resin film 40 is desirable: the resin film 40 iscapable of being separated from the lead frame after the resin sealingby reducing the adhesive strength by heat treatment, chemical processingor UV (ultraviolet) radiation, retains appropriate physical positions(pitch) of the first and second signal connection leads 14 a, 14 b,withstands appropriate deformation at a high temperature in the step ofconnecting the thin metal wires, is recoverable at normal temperature,and is resistant to high-temperature environment in the step ofconnecting the thin metal wires and the resin sealing step.

[0045] An adhesive resin film primarily containing polyimide and havinga thickness of 25 μm was used as the resin film 40 in the presentembodiment.

[0046] The resin film used in the embodiment of the present invention isa tape formed from a polyimide film and a thermoplastic, polyimide-basedadhesive attached thereto. In order to achieve the object of the presentinvention, this tape has an elongation of about 5 ppm/° C. to about 25ppm/° C. at normal temperature and at a heating temperature of around200° C., and has a thickness of about 25 μm so as to stably fit onprojections of a heat plate (heating block) described below.

[0047]FIG. 3A is a plan view of a region of the lead frame 10 forpackaging a single semiconductor chip. FIG. 3B is a cross-sectional viewtaken along line IIIb-IIIb in FIG. 3A extending through the first signalconnection leads 14 a. FIG. 3C is a cross-sectional view taken alongline IIIc-IIIc in FIG. 3A extending through the second signal connectionleads 14 b. The lead frame 10 includes an array of a multiplicity ofregions for packaging a single semiconductor chip as shown in FIGS. 3Ato 3C.

[0048] As shown in FIG. 3A, the lead frame 10 includes a die pad 11, anouter frame 13 surrounding the die pad 11, four suspension leads 12extending from the outer frame 13, for supporting the die pad 11 at eachcorner, and first signal connection leads 14 a and second signalconnection leads 14 b both extending from the outer frame 13 toward thedie pad 11.

[0049] It should be noted that a dam bar connecting the signalconnection leads 14 a and 14 b together may be provided along the innerside of the outer frame 13.

[0050] As shown in FIG. 3B, each of the first signal connection leads 14a has an external terminal 15 a at the tip, and a region from theconnection with the outer frame 13 (or dam bar) to the external terminal15 a corresponds to a half-etched portion Phe.

[0051] As shown in FIG. 3C, each of the second signal connection leads14 b has an external terminal 15 b near the connection with the outerframe 13 (or dam bar), and a region from the connection with the outerframe 13 (or dam bar) to the external terminal 15 b and a region fromthe external terminal 15 b to the tip correspond to a half-etchedportion Phe.

[0052] It should be noted that the term “half-etched” as used hereinmeans that each signal connection lead 14 a, 14 b is partially etchedaway in the thickness direction, and does not mean that each signalconnection lead 14 a, 14 b is etched away by half the thickness.

[0053] The lead frame 10 does not include any tie bar for preventingoutflow of the sealing resin in the resin sealing step. The lead frame10 of the present embodiment is a lead frame plated with three metallayers. More specifically, the lead frame 10 is a frame of a copper (Cu)material plated with a nickel (Ni) layer as underplating, a palladium(Pd) layer thereon, and a thin gold (Au) layer as the uppermost layer.It should be noted that, in addition to the copper (Cu) material, amaterial such as 42-alloy material may be used, and the lead frame 10may be plated with a noble metal other than nickel (Ni), palladium (Pd)and gold (Au). Moreover, the frame is not necessarily plated with threelayers.

[0054] Then, in the step shown in FIG. 2B, a semiconductor chip 20 isfixed to the die pad 11 of the lead frame 10 by an adhesive layer 17.This step is a so-called die bonding step.

[0055] Thereafter, in the step shown in FIG. 2C, the electrode pads 21of the semiconductor chip 20 mounted on the die pad 11 are electricallyconnected to the first and second signal connection leads 14 a, 14 b bythe thin metal wires 25, respectively. At this time, the load of about40 g to about 60 g is normally applied from a bonding tool in order topress the thin metal wires. This step is a so-called wire bonding step.This wire bonding step is conducted with the outer frame of the leadframe being pressed from above.

[0056]FIG. 4A is a plan view of the lead frame and the semiconductorchip after wire bonding. FIG. 4B is a cross-sectional view taken alongline Ivb-IVb in FIG. 4A extending through the first signal connectionleads 14 a. FIG. 4C is a cross-sectional view taken along line IVc-IVcin FIG. 4A extending through the second signal connection leads 14 b.

[0057] As shown in FIGS. 4A to 4C, the semiconductor chip 20 is mountedon the die pad 11 of the lead frame 10 with the adhesive layer 17interposed therebetween. The thin metal wires 25 are connected to thefirst signal connection leads 14 a at the half-etched portions Phe, andto the second signal connection leads 14 b at a position right above theexternal terminals 15 b. It should be noted that the thin metal wires 25may be connected to the second signal connection leads 14 b at thehalf-etched portions Phe.

[0058] Then, in the step of FIG. 2D, the lead frame 10 with thesemiconductor chips 20 mounted thereon and the resin film 40 attachedthereto is mounted in a sealing mold 60 formed from a lower mold 61 andan upper mold 62 having a large die cavity 63. At this time, a pluralityof semiconductor chips 20 are accommodated in a single die cavity 63.Resin sealing is conducted as follows: a sealing resin is introducedinto the die cavity 63 of the sealing mold 60 with the outer frame 13 ofthe lead frame 10 and the resin film 40 being pressed with the sealingmold 60. The semiconductor chips 20, die pads 11, signal connectionleads 14 a, 14 b, thin metal wires 25 and the like are thus sealedwithin the sealing resin 30.

[0059] Thereafter, in the step of FIG. 2E, the resin film 40 attached tothe back surface of the die pads 11, first and second signal connectionleads 14 a, 14 b and sealing resin 30 is subjected to heat treatment,chemical processing, UV radiation or the like in order to reduce theadhesive strength of the resin film 40. The resin film 40 is then peeledoff. The sealed structure is thus formed in which the respective lowersurfaces of the first and second external terminals 15 a, 15 b and thedie pad 11 are exposed from the back surface of the sealing resin 30without being covered with the sealing resin.

[0060] Finally, the respective base ends of the first and second signalconnection leads 14 a, 14 b connected to the outer frame 13 are cut witha cutting blade such that the cutting plane is substantially flush withthe side surface of the sealing resin 30. The resin-sealed semiconductordevice is thus completed in which the external terminal portions 15 a,15 b and the die pad 11 are exposed from the lower surface of thesealing resin 30.

[0061] Note that, as a method for locating the upper surface of the diepad 11 higher than the upper surfaces of the first and second signalconnection leads 14 a, 14 b, each suspension lead 12 in FIG. 3A may havea bent portion formed by pressing or the like so as to locate the diepad 11 higher than other parts of the lead frame. As a result, a gap isformed between the resin film 40 and the die pad 11, whereby the sealingresin reaches the back surface of the die pad 11 in the resin sealingstep. In this case, this improves the holding power of the sealing resin30 for holding the die pad 11, resulting in improved reliability. Itshould be noted that, in the case where the back surface of the die pad11 is exposed from the sealing resin 30 as in the present embodiment,this improves heat dissipation to the mounting substrate.

[0062]FIGS. 5A to 5C are cross-sectional views specifically illustratingthe wire bonding step in the embodiment of the present invention.

[0063] First, in the step of FIG. 5A, a heat plate (heating block) 50 isprepared as a jig for conducting wire bonding. The heat plate 50 hasprojections 51 for supporting the half-etched portions Phe of the firstsignal connection leads 14 a. The lead frame 10 having the resin film 40attached thereto is mounted on the heat plate 50. One end of a thinmetal wire is connected to the corresponding electrode pad 21 of thesemiconductor chip 20 by a bonding tool 55 while heating thesemiconductor chip 20 by the heat plate 50.

[0064] Thereafter, in the step of FIG. 5B, the other end of the thinmetal wire 25 is connected to the half-etched portion Phe of thecorresponding first signal connection lead 14 a. At this time, theportion of the projection 51 of the heat plate 50 supporting the firstsignal connection lead 14 a corresponds to the portion of the firstsignal connection lead 14 a to which the other end of the thin metalwire 25 is connected. In order to connect the thin metal wires 25 to thefirst and second signal connection leads 14 a, 14 b, it is necessary toheat the respective joints and apply the pressing force of normallyabout 40 g to about 60 g to the thin metal wires 25 by the bonding tool55. Since the heating plate 50 having the projections 51 is used in thepresent embodiment, the pressing force and the heat can be effectivelyapplied to the joints while preventing deformation of the half-etchedportions Phe even when the thin metal wires are connected to thehalf-etched portions Phe of the signal connection leads 14 a, 14 b.

[0065] Note that, in the present embodiment, the thin metal wires areconnected to the second signal connection leads 14 b at a position rightabove the respective external terminals 15 b. Therefore, the heat plate50 does not have any projection for supporting the half-etched portionsof the second signal connection leads 14 b. It should be noted that, inthe case where the thin metal wires are connected to the half-etchedportions Phe of the second signal connection leads 14 b, projections forsupporting the half-etched portions of the second signal connectionleads 14 b are provided in the heat plate 50.

[0066] As shown in FIG. 5C, all the electrode pads 21 of thesemiconductor chip 20 are respectively connected to the signalconnection leads 14 a, 14 b by the thin metal wires 25. The wire bondingstep is thus completed.

[0067] In general, in order to connect the thin metal wires 25 to thefirst and second signal connection leads 14 a, 14 b, it is necessary toheat the respective joints and apply the pressing force to the thinmetal wires 25 by the bonding tool 55. When the thin metal wires areconnected to the half-etched portions Phe of the signal connection leads14 a, 14 b, the half-etched portions Phe may possibly be deformed. Evenif the deformation is within the range of elastic deformation, bendingof the half-etched portions Phe would hinder the pressing force frombeing effectively applied to the joints, thereby possibly degradingreliability of the connections. In the present invention, however, whenthe thin metal wires are connected to the half-etched portions Phe ofthe signal connection leads (in the present embodiment, the first signalconnection leads 14 a) in the wire bonding step, conducting the wirebonding by using the heat plate (jig) having the projections 51 atpositions corresponding to the half-etched portions Phe ensuresreliability of the connection between the thin metal wires and thesignal connection leads. Moreover, in the case where the wire bonding isconducted with the resin film 40 being attached to the lead frame 10,the heat of the heat plate 50 can be efficiently transmitted to thesignal connection leads (the first signal connection leads 14 a) withthe resin film 40 being stretched tight. This also ensures reliabilityof the connection by the wire bonding.

[0068] As a result, the limitations on the position of the externalterminals 15 a, 15 b in the signal connection leads 14 a, 14 b can bereduced, allowing for increase in the number of external terminals. Inparticular, arranging the external terminals 15 a of the first signalconnection leads 14 a under the semiconductor chip 20 as in the presentembodiment allows for significant increase in the number of externalterminals.

[0069] First Modification

[0070] Hereinafter, various modifications of the embodiment of thepresent invention will be described.

[0071]FIG. 6 is a cross-sectional view illustrating the case where thewire bonding step is conducted without attaching the resin film 40 tothe lead frame 10 according to the first modification of the embodimentof the present invention. As shown in FIG. 6, in this case, eachprojection 51 of the heat plate 50 directly contact the half-etchedportion Phe of the corresponding first signal connection lead 14 a. Thisenables the pressing force of the bonding tool 55 to be applied to thethin metal wire 25 while preventing deformation of the half-etchedportion Phe of the first signal connection lead 14 a, ensuringreliability of the connection. Note that the wire bonding step isconducted with the outer frame of the lead frame being pressed by thejig.

[0072] Second Modification

[0073]FIG. 7 is a cross-sectional view illustrating only the wirebonding step according to the second modification of the embodiment ofthe present invention.

[0074] In the present modification, wire bonding is conducted using aheat plate 50 having a vacuuming hole 52 near the projection 51. At thistime, the jig presses the outer frame of the lead frame, but not up tothe upper portions of the signal connection leads 14 a, 14 b. However,the resin film 40 around the projection 51 is pulled downward byvacuuming, enabling slacking in the resin film 40 to be effectivelyeliminated.

[0075] Third Modification

[0076]FIG. 8 is a cross-sectional view illustrating only the wirebonding step according to the third modification of the embodiment ofthe present invention.

[0077] A heat plate 50 used in the present modification is tilted suchthat the upper surface of the region inside the projection 51 is locatedhigher than that of the region outside the projection 51 by a height H1.Moreover, the upper surface of the region under the die pad 11 islocated higher than that of the peripheral region by a height H2. Inother words, the upper surface of the region of the heat plate 50 underthe die pad 11 is located higher than that of the region outside theprojection 51 by the height (H1+H2). This height (H1+H2) is set so thatthe resin film 40 hardly slacks when stretched by thermal expansion. Atthis time, the outer frame of the lead frame is pressed by the jig. Thusstretching the resin film 40 to the minimum required degree enables therelative positions (pitch) of the external terminals 15 a, 15 b afterresin sealing to be stably made within the design range whilesuppressing slacking in the resin film 40.

[0078] Fourth Embodiment

[0079]FIG. 9 is a cross-sectional view illustrating only the wirebonding step according to the fourth modification of the embodiment ofthe present invention.

[0080] In the present modification, wire bonding is conducted using aheat plate 50 which includes, in addition to the structure of the thirdmodification, a vacuuming hole 52 near the projection 51 and a vacuuminghole 53 near the projection 56. The resin film 40 around the projections51, 56 is pulled downward, enabling slacking in the resin film 40 to beeffectively eliminated.

[0081] Fifth Modification

[0082]FIG. 10 is a cross-sectional view illustrating only the wirebonding step according to the fifth modification of the embodiment ofthe present invention.

[0083] A heat plate 50 used in the present modification has a projection56 under the die pad 11 in addition to the projections 51, so that theupper surface of the region under the die pad 11 is located higher thanthe upper surfaces of the other regions. It should be noted that theheat plate 50 in the present modification is not tilted such that theupper surface of the region inside the projection 51 is located higherthan that of the region outside the projection 51 by the height H1 as inthe third modification. The outer frame of the lead frame is pressed bythe jig.

[0084] In the present modification as well, the resin film 40 is raisedupward by the projections 51, 56, enabling slacking in the resin film 40to be effectively eliminated.

[0085] Sixth Modification

[0086]FIG. 11 is a cross-sectional view illustrating only the wirebonding step according to the sixth modification of the embodiment ofthe present invention.

[0087] In the present modification, wire bonding is conducted using aheat plate 50 that includes, in addition to the structure of the fifthmodification, a vacuuming hole 52 near the projection 51 and a vacuuminghole 53 near the projection 56. The outer frame of the lead frame ispressed by the jig. The resin film 40 around the projections 51, 56 ispulled downward by vacuuming, enabling slacking in the resin film 40 tobe effectively eliminated and also suppressing separation of the signalconnection leads 14 a, 14 b from the heat plate 50 that would otherwiseoccur as the signal connection leads 14 a, 14 b are pulled by the resinfilm 40.

[0088] Seventh Modification

[0089]FIG. 12 is a cross-sectional view illustrating only the wirebonding step according to the seventh modification of the embodiment ofthe present invention.

[0090] A heat plate 50 used in the present modification includes, inaddition to the projections 51, a tall projection 56 under the die pad11, so that the upper surface of the region under the die pad 11 islocated much higher than the upper surfaces of the other regions. Theprotruding amount of the projection 56 is set so that the suspensionleads 12 in FIG. 3A are plastically deformed to locate the die pad 11higher than other parts of the lead frame.

[0091] On the other hand, in the third to sixth modifications, theprojection 56 raises the die pad 11 high during the wire bonding. Afterthe wire bonding, however, the die pad 11 springs back so that the lowersurface of the die pad 11 is substantially flush with the lower surfaceof each signal connection lead 14 a, 14 b. In other words, in the thirdto sixth modifications, the height of the projection 56 is set so thatthe suspension leads 12 in FIG. 3A are only elastically deformed withoutbeing plastically deformed in the wire bonding step. At this time, theouter frame of the lead frame is pressed by the jig.

[0092] The heat plate 50 has a vacuuming hole 52 near the projection 51and a vacuuming hole 53 near the projection 56.

[0093] Accordingly, in the present modification, the lower surface ofthe die pad 11 is separated from the resin film 40 in the resin sealingstep after the wire bonding. As a result, the sealing resin reaches thelower surface of the die pad 11 in the resin sealing step. This improvesthe holding power of the sealing resin 30 for holding the die pad 11,and also enables introduction of moisture and the like through theinterface between the die pad 11 and the sealing resin 30 to besuppressed. In other words, in the case where the die pad 11 is to belocated higher than the signal connection leads 14 a, 14 b, the presentmodification enables operations such as pressing the lead frame 10 inadvance to be omitted, allowing for reduced manufacturing costs.

[0094] Moreover, according to the present modification, the resin film40 around the projections 51, 56 is pulled downward, enabling slackingin the resin film 40 to be effectively eliminated and also suppressingseparation of the signal connection leads 14 a, 14 b from the heat plate50 that would otherwise occur as the signal connection leads 14 a, 14 bare pulled by the resin film 40.

[0095] Eighth Modification

[0096]FIG. 13 is a bottom view of a resin-sealed semiconductor deviceaccording to the eighth modification regarding a method for arrangingthe signal connection leads 14 a, 14 b. As shown in FIG. 13, in thisexample, the external terminals 15 a, 15 b is approximately square intransverse section. The outer side surface of each first externalterminal 15 a is approximately flush with the side surface of thesealing resin 30. The second signal connection leads 14 b are arrangedin line at a predetermined distance inward from the side surface of thesealing resin 30.

[0097] According to the present modification, the external terminals arearranged as outside as possible, allowing for reduction in package sizewhile increasing the number of external terminals.

[0098] As has been described above, the embodiment of the presentinvention and the modifications thereof enable the thin metal wires tobe connected to the half-etched portions Phe. This allows for stableproduction of a resin-sealed semiconductor device with reduced size andthickness and improved performance, making it possible to deal withvarious semiconductor devices.

[0099] Moreover, the step of attaching the resin film 40 to the leadframe 10 can be used in common regardless of the size of thesemiconductor device, the number of lands, and the pitch, therebyimproving the productivity. This enables connection of the thin metalwires in a semiconductor device incorporating a die pad therein andhaving a small distance (pitch) between the external terminals, or asemiconductor device having an exposed die pad and having a smalldistance (pitch) between the external terminals.

[0100] Further, according to the manufacturing method of the presentembodiment, a plurality of semiconductor chips are mounted in a largedie cavity, and after sealing, the resultant structure is cut intoresin-sealed semiconductor devices each incorporating a singlesemiconductor chip. This enables improvement in productivity and alsoenables the use of a common mold sized for the resin-sealedsemiconductor devices. Moreover, the resin film 40 is attached inadvance to the lower surface of the die pad 11, the back surfaces of thefirst and second signal connection leads 14 a, 14 b (the first andsecond external terminals 15 a, 15 b) and the like prior to the resinsealing step. As a result, the sealing resin 30 will not reach thesesurfaces in the sealing step, preventing a resin bur from being formedat the back surfaces of the die pad 11 and the first and second externalterminals 15 a, 15 b.

[0101] Moreover, the use of a method for resin-sealing a multiplicity ofsemiconductor chips in a common die cavity eliminates the need for thestep of cutting with a mold after the resin sealing step. Accordingly,the signal connection leads 14 a, 14 b will not be separated due to thecutting stresses applied to the interface between the sealing resin 30and the signal connection leads 14 a, 14 b. Further, the followingproblems can be prevented: reduction in yield in the cutting step due tofalling of a resin bur produced at each cutting plane of the signalconnection leads 14 a, 14 b; poor contact in the inspection step; poorconnection due to falling of a resin bur during mounting; and generationof defects resulting from wear of the cutting mold.

[0102] Note that the present invention is not limited to the method ofthe above embodiment. For example, various combinations of themodifications of the present embodiment allow for reliable selection ofboth the number of external terminals arranged in a matrix and thearrangement thereof in a semiconductor device, which are suitable forthe size of a semiconductor chip and the number of pads.

[0103] The present invention is also applicable to a die pad portion ofa semiconductor device of SON (small outline non-leaded package) and QFPincorporating a die pad therein. In this case, connection between thesemiconductor chip and the thin metal wires is improved.

[0104] Moreover, although increasing the costs, solder balls may beprovided in order to manufacture a narrower-pitch semiconductor deviceand to mount such a semiconductor device on a printed board.

What is claimed is:
 1. A method for manufacturing a resin-sealedsemiconductor device, comprising the steps of: (a) preparing a leadframe including a die pad on which a semiconductor chip is mounted, aframe arranged outside the die pad, and a plurality of leads extendingfrom the frame toward the die pad and each including a half-etchedportion; (b) mounting on the die pad of the lead frame the semiconductorchip including a plurality of electrode pads; (c) mounting the leadframe having the semiconductor chip mounted thereon on a jig includingprojections for supporting the half-etched portions of the leads towhich thin metal wires are respectively connected out of the half-etchedportions of the plurality of leads; (d) connecting the electrode pads ofthe semiconductor chip to the plurality of leads by the thin metalwires, respectively; and (e) resin-sealing the semiconductor chip, thedie pad, the leads and the thin metal wires with a resin film beingpressed against a lower surface of the lead frame, wherein, in the step(d), the half-etched portions to which the thin metal wires areconnected are supported by the projections of the jig, respectively. 2.The method according to claim 1, wherein the step (d) is conducted withthe heated jig.
 3. The method according to claim 3, wherein the resinfilm is mounted to the lower surface of the lead frame prior to the step(c), and the step (d) is conducted with the resin film being mounted tothe lower surface of the lead frame.
 4. The method according to claim 3,wherein, in the step (d), the jig including a vacuuming opening is usedto draw the resin film toward a surface of the jig by vacuuming.
 5. Themethod according to claim 3, wherein, in the step (d), the die pad ofthe lead frame is raised upward.
 6. The method according to claim 3,wherein a material having a thermal expansion coefficient of 5 to 25×10ppm/° C. is used as the resin film.
 7. The method according to claim 1,wherein, in the step (a) or (c), an upper surface of the die pad of thelead frame is located higher than respective upper surfaces of theleads.
 8. The method according to claim 1, wherein, in the step (a), theplurality of leads of the lead frame are arranged such that respectivelower portions of the plurality of leads except for the half-etchedportions are arranged in a plurality of lines when viewed from a backsurface of the sealing resin.